The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop with finer adjustability and, thus, reduced jitter.
For achieving a high-speed operation in a semiconductor memory device, a synchronous dynamic random access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.
Generally, when data are outputted in synchronization with the external clock signal, a skew occurs between the external clock signal and the output data. In the SDRAM, a delay locked loop (DLL) can be used to compensate for the skew that occurs between either an external clock signal and an output data, or an external clock signal and an internal clock signal.
FIG. 1 is a block diagram of a conventional DLL. Referring to FIG. 1, the illustrated conventional DLL includes a clock buffer 100, a delay monitor 110, a phase detector 120, a shift register 130 and a digital delay line 140.
The clock buffer 100 receives an external clock EXT_CLK to generate an internal clock CLK_IN. The delay monitor 110 receives a DLL clock DLL_CLK, i.e., an output of the DLL, to perform a monitoring operation and to add a predetermined amount of delay for determining a delay amount of the internal clock CLK_IN. An output of the delay monitor 110 is fed back to the phase detector 120.
The phase detector 120 compares a phase difference between the internal clock CLK_IN and the output of the delay monitor 110 to generate either a shift-left signal SHF_L or a shift-right signal SHF_R as a control signal depending on whether less or more delay is desired.
The shift register 130 decreases the delay amount in response to the shift-left signal SHF_L and increases the delay amount in response to the shift-right signal SHF_R. The digital delay line 140 delays the internal clock CLK_IN according to an output of the shift register 130 to generate the DLL clock DLL_CLK.
In FIG. 2, there is shown an exemplary diagram of the digital delay line having three delay units, generally shown as 230, 231, and 232. As shown in FIG. 2, the illustrated digital delay line 140 includes a control unit 200 for transferring the internal clock CLK_IN through a number of the delay units 230, 231, 232 in response to a first, a second, and a third shift control signals, generally shown as SL1, SL2, and SL3, respectively. The digital delay line 140 also includes a delay unit 210 for performing a time delay operation under control of the control unit 200. The digital delay line 140 further includes an output unit 220 for receiving an output of the delay unit 210 to generate the DLL clock DLL_CLK.
When only the first shift control signal SL1 is a logic high, the digital delay line 140 generates the DLL clock DLL_CLK obtained by delaying the internal clock CLK_IN through only a first delay unit 230. Then, the DLL clock DLL_CLK is transferred to the phase detector 120 through the delay monitor 110, and the phase detector 120 compares a phase of the DLL clock DLL_CLK and that of the internal clock CLK_IN.
If the internal clock CLK_IN needs further delay, the phase detector 120 activates the shift-right signal SHF_R. As a result, the first and the second shift control signals SL1 and SL2 are set to a logic low and a logic high, respectively. That is, the logic high is shifted in a right direction from SL1 to SL2.
Then, the digital delay line 140 generates the DLL clock DLL_CLK obtained by delaying the internal clock CLK_IN by two delay units 230 and 231. The DLL clock DLL_CLK is again fed back to the phase detector 120 through the delay monitor 110.
Meanwhile, if it is needed to delay the internal clock CLK_IN less, the phase detector 120 activates the shift-left signal SHF_L. As a result, the logic high signal is shifted in a left direction.
However, since each delay unit contained in the conventional digital delay line 140 is implemented with two NAND gates, the conventional DLL can make only relatively large, coarse adjustments, for example, adjustments of about several picoseconds. Therefore, as the semiconductor memory device operates at a faster speed, there is a need for a DLL with finer adjustability.